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lc 2 mos quad spst switches data sheet adg211a/ adg212a rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2012 analog devices, inc. all rights reserved. technical support www.analog.com features 44 v supply maximum rating 15 v analog signal range low r on : 115 maximum low leakage: 0.5 na typical break-before-make switching single supply operation possible extended plastic temperature range: ?40c to +85c ttl/cmos compatible available in 16-lead pdip/soic and 20-pead plcc packages pin compatible to dg211/dg212 functional block diagram figure 1. figure 2. general description the adg211a and adg212a are monolithic cmos devices comprising four independently selectable switches. they are designed on an enhanced lc 2 mos process, which gives an increased signal handling capability of 15 v. these switches also feature high switching speeds and low r on . the adg211a and adg212a consist of four spst switches. they differ only in that the digital control logic is inverted. in multiplexer applications, all switches exhibit break-before-make switching action when driven simultaneously. inherent in the design is low charge injection for minimum transients when switching the digital inputs. product highlights 1. extended signal range. these switches are fabricated on an enhanced lc 2 mos process, resulting in high breakdown and an increased analog signal range of 15 v. 2. single supply operation. for applications where the analog signal is unipolar (0 v to 15 v), the switches can be operated from a single 15 v supply. 3. low leakage. leakage currents in the range of 500 pa make these switches suitable for high precision circuits. the added feature of break-before-make allows for multiple outputs to be tied together for multiplexer applications while keeping leakage errors to a minimum. notes 1. switches shown for a logic 1 input. adg211a in1 in2 in3 in4 s1 d1 s2 d2 s3 d4 s4 d3 10950-001 notes 1. switches shown for a logic 1 input. adg212a in1 in2 in3 in4 s1 d1 s2 d2 s3 d4 s4 d3 10950-002
adg211a/adg212a data sheet rev. c | page 2 of 16 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 gene ral description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specificatio ns ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution ...................................................................................4 pin configurations and function descriptions ............................5 typical performance characteristics ..............................................6 ter mi nolo g y .......................................................................................9 test circuits ..................................................................................... 10 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 13 revision history 10/12 rev. b to rev. c updated format .................................................................. universal added pin descriptions, table 3 .................................................... 5 moved tabl e 4 ................................................................................... 5 changes to figure 5, figure 6, figure 8, and figure 9 ................. 6 updated outline dimensions ....................................................... 13 changes to ordering guide .......................................................... 14 9/02 rev. a t o rev. b
data sheet adg211a/adg212a rev. c | page 3 of 16 specifications v dd = + 15 v , v ss = ? 15 v , v l = 5 v, unless otherwise noted. table 1. parameter 25c ? 40c to +85c unit test conditions /comments min typ max min typ max analog switch analog signal range 15 15 v r on 115 175 ?10 v v s +10 v, i ds = 1 ma, see figure 21 r on vs. v d (v s ) 20 % r on drift 0.5 %/c r on match 5 % v s = 0 v, i ds = 1 ma lea kage currents i s (off ) 0.5 na v d = 14 v; v s = ? 14 v; see figure 22 off input leakage 5 100 na i d (off ) 0.5 na v d = 14 v; v s = ? 14 v; see figure 22 off output leakage 5 100 na i d (on) 0.5 na v d = v s = 14 v; see figure 23 on channel leakage 5 200 na digital control v inh , input high voltage 2.4 v ttl compatibility is independent of v l v inl , input low voltage 0.8 v i nl or i nh 1 a c in , digital input capacitance 5 pf dyn amic characteristics t open 1 30 ns see figure 24 t on 1 600 ns see figure 25 t of f 1 450 ns see figure 25 off isolation 80 db v s = 10 v (p - p); f = 100 khz; r l = 75 ; see figure 26 channel - to - channel crosstalk 80 db see figure 27 c s (off ) 5 pf c d (off ) 5 pf c s , c d (on) 16 pf q inj , charge injection 20 pc r s = 0 ; c l = 1000 pf; v s = 0 v; see figure 28 power supply i dd 0.6 ma digital inputs = v inl or v inh i dd 1 ma i ss 0.1 ma i ss 0.2 ma i l 0.9 ma 1 sample tested at 25c to ensure compliance.
adg211a/adg212a data sheet rev. c | page 4 of 16 absolute maximum ratings t a = 25c, unless otherwise stated. table 2. parameter rating v dd to v ss 44 v v dd to gnd 25 v v ss to gnd ?25 v v l to gnd ?0.3 v, 25 v analog inputs 1 voltage at s, d v ss ? 0.3 v to v dd + 0.3 v continuous current, s or d 30 ma pulsed current s or d 1 ms duration, 10% duty cycle 70 ma digital inputs 1 voltage at in v ss ? 2 v to v dd + 2 v or 20 ma, whichever occurs first power dissipation (any package) up to +75c 470 mw derates above +75c by 6 mw/c operating temperature ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering 10 sec) +300c 1 overvoltage at in, s, or d will be clamped by diodes. current should be limited to the maximum rating listed in table 2. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet adg211a/adg212a rev. c | page 5 of 16 pin configuration s and function descrip tions figure 3. p dip, soic pin configuration figure 4. plcc pin configuration table 3 . pin function descriptions pin no. mneonic description p d i p, soic plcc 1 2 in1 logic control input. 2 3 d1 drain terminal. can be an input or output. 3 4 s1 source terminal. can be an input or output. 4 5 v ss most negative power supply potential. 5 7 gnd ground (0 v) reference. 6 8 s4 source terminal. can be an input or output. 7 9 d4 drain terminal. can be an input or output. 8 10 in4 logic control input. 9 12 in3 logic control input. 10 13 d3 drain terminal. can be an input or output. 11 14 s3 source terminal. can be an input or output. 12 15 v l logic supply voltage . 13 17 v dd most positive power supply potential. 14 18 s2 source terminal. can be an input or output. 15 19 d2 drain terminal. can be an input or output. 16 20 in2 logic control input. 1, 6, 11, 16 nic no internal connection. table 4 . truth table ad211a in ad212a in sitch conition 0 1 on 1 0 off in1 1 d1 2 s1 3 v ss 4 in2 16 d2 15 s2 14 v dd 13 gnd 5 s4 6 d4 7 v l 12 s3 11 d3 10 in4 8 in3 9 adg211a/ adg212a top view (not to scale) 10950-003 notes 1. nic = no internal connection. 1 20 19 23 4 5 6 7 8 18 17 16 15 14 9 10 11 12 13 s1 v ss nic gnd s4 s2 v dd nic v l s3 d1 in1 nic in2 d2 d4 in4 nic im3 d3 pin 1 indentfier adg211a/ adg212a top view (not to scale) 10950-004
adg211a/adg212a data sheet rev. c | page 6 of 16 typical performance characteristics the switches can comfortably operate anywhere in the 10 v to 15 v single or dual supply range, with only a slight degradation in performance. the following graphs show the relevant performance curves. the test circuits and test conditions are given in a following section, test circuits . figure 5 . r on as a function of v d (v s ), dual 15 v supplies figure 6 . r on as a function of v d (v s ), dual 10 v supplies figure 7 . leakage current as a function of temperature (note that leakage current reduces as the supply voltages reduce) figure 8 . r on as a function of v d (v s ), single +15 v supply figure 9 . r on as a function of v d (v s ), single +10 v supply figure 10 . trigger levels vs. power supply voltage, dual or single supply voltage 120 0 30 60 90 ?15 ?10 ?5 0 5 10 15 r on () v d (v s ) (v) v dd = +15v v ss = ?15v 70c 25c 0c 10950-005 120 0 30 60 90 ?10 ?5 0 5 10 r on () v d (v s ) (v) v dd = +10v v ss = ?10v 70c 25c 0c 10950-006 100 10 1 0.1 0.01 20 90 80 70 60 50 40 30 current (na) temperature (c) v dd = +15v v ss = ?15v i d (on) i d (off) i s (off) 10950-007 120 0 30 60 90 0 5 10 15 r on () v d (v s ) (v) v dd = 15v v ss = 0v 70c 25c 0c 10950-008 150 0 30 60 90 120 0 5 10 r on () v d (v s ) (v) v dd = 10v v ss = 0v 70c 25c 0c 10950-009 2.5 2.0 1.5 1.0 0.5 0 10 11 12 13 14 15 trigger level (v) supply voltage (v) temp = 0c to 70c 10950-010
data sheet adg211a/adg212a rev. c | page 7 of 16 figure 11 . t on vs. supply voltage (dual supply) figure 12 . t o ff vs. supply voltage (dual supply) figure 13 . off isolation and channel - to - channel crosstalk vs. supply voltage figure 14 . t on vs. supply voltage (single supply) figure 15 . t o ff vs. supply voltage (single supply) figure 16 . charge injection vs. source voltage (v s ) for dual and single 15 v supplies 220 80 100 120 140 160 180 200 10 11 12 13 14 15 t on (ns) supply voltage (v) 70c 25c 0c 10950-0 11 80 60 40 20 0 10 11 12 13 14 15 t off (ns) supply voltage (v) 70c 25c 0c 10950-012 50 60 70 80 90 10 11 12 13 14 15 off isolation (db) supply voltage (v) single supply dual supply 10950-013 220 80 100 120 140 160 180 200 10 11 12 13 14 15 t on (ns) supply voltage (v) 70c 25c 0c 10950-014 80 60 40 20 0 10 11 12 13 14 15 t off (ns) supply voltage (v) 70c 25c 0c 10950-015 60 40 20 0 ?20 ?40 ?16 ?12 ?8 ?4 0 4 8 12 16 charge injection (pc) v s (v) v dd = +15v v ss = ?15v v dd = +15v v ss = 0v 10950-016
adg211a/adg212a data sheet rev. c | page 8 of 16 figure 17 . charge injection vs. source voltage for dual and single 10 v supplies figure 18 . i ss vs. supply voltage (dual supply) figure 19 . i dd vs. supply voltage, (dual supply) figure 20 . i dd vs. supply voltage (single supply) 60 ?40 ?20 0 20 40 ?16 ?12 ?8 ?4 0 4 8 12 16 charge injection (pc) v s (v) v dd = +10v v ss = ?10v v dd = +10v v ss = 0v 10950-017 0.4 0 0.1 0.2 0.3 10 15 14 13 12 11 i ss (a) supply voltage (v) 0c 25c 70c 10950-018 0.7 0.6 0.5 0.4 0.3 0.2 0.1 10 11 12 13 14 15 i dd (ma) supply voltage (v) 0c 25c 70c 10950-019 0.7 0.6 0.5 0.4 0.3 0.2 0.1 10 11 12 13 14 15 i dd (ma) supply voltage (v) 0c 25c 70c 10950-020
data sheet adg211a/adg212a rev. c | page 9 of 16 terminology r on ohmic resistance between the out and s terminals. r on match difference between the r on of any two channels . i s (off) source terminal leakage current when the switch is off . i d (off) drain terminal leakage current when the switch is off . i d (on) leakage current that flows from the closed switch into the body . v d (v s ) analog voltage on the d, s terminals. c s (off) switch input capacitance off condition . c d (off) switch output capacitance off condition . c in digital input capacitance . c d , c s (on) input or output capacitance when the switch is on . t on delay time between the 50% and 90% points of the digital input and switch on condition . t off delay time between the 50% and 90% points of the digital input and switch off condition . t open off time measured between 50% points of both switches, which are connected as a multiplexer when switching from one address state to another . v inl maximum input voltage for a logic low . v inh minimum input voltage for a logic high . i inl (i inh ) input current of the digital input . v dd most positive voltage supply . v ss most negative voltage supply . v l logic supply voltage . i dd positive supply current . i ss negative supply current .
adg211a/adg212a data sheet rev. c | page 10 of 16 test circuits figure 21. figure 22. figure 23. figure 24. figure 25. i ds v1 s v s r on = v1/i ds d 10950-021 sd v d v s i d (off) i s (off) a a 10950-022 sd v d v s i d (on) a 10950-023 +5v v l +15 v v dd 2v v in gnd v ss ?15v v out d1 s1 d2 s2 in1 in2 14pf 330 ? * * * both the buffer and inverter should have the same propagation delay. adg211a adg212a v out v in 3v v in 3v 50% t open 10950-024 +5v v l v dd v dd 2v gnd v ss v ss v out d s in v in 14pf 330 ? 50% 50% 50% 50% 90% 90% adg211a adg212a v in v in v out 3v 3v t on t off 10950-025
data sheet adg211a/adg212a rev. c | page 11 of 16 figure 26 . off isolation figure 27 . channel - to - channel crosstalk figure 28 . charge injection v ss v dd v dd v s +5v v l gnd v ss v out d s v in r l 75? adg211a: v in = 5v adg212a: v in = 0v off isolation = 20 log |v s /v out | 10950-026 v dd v dd +5v v l v ss gnd v ss v in r l 75? adg211a: v in = 0v adg212a: v in = 5v channel-to-channel crosstalk = 20 log |v s /v out | v s d s v in 75? s d nc v out 10950-027 v in v out 5v 0v v out q inj = c l v out v s v out d s c l 1f v in ad711 r s v dd v dd +5v v l v ss gnd v ss 10950-028
adg211a/adg212a data sheet rev. c | page 12 of 16 outline dimensions figure 29. 16-lead plastic dual in-line package [pdip] narrow body (n-16) dimensions shown in inches and (millimeters) figure 30.16-lead standard small outline package [soic_n] narrow body (r-16) dimensions shown in millimeters and (inches) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001-ab 073106-b 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 16 1 8 9 0.100 (2.54) bsc 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ac 10.00 (0.3937) 9.80 (0.3858) 16 9 8 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 060606-a 45
data sheet adg211a/adg212a rev. c | page 13 of 16 figure 31. 20-lead plastic leaded chip carrier [plcc] (p-20) dimensions shown in inches and (millimeters) ordering guide model 1 temperature range package description package option adg211akn ?40c to +85c 16-lead pdip n-16 adg211aknz ?40c to +85c 16-lead pdip n-16 ADG211AKPZ ?40c to +85c 20-lead plcc p-20 adg211akr ?40c to +85c 16-lead soic_n r-16 adg211akrz ?40c to +85c 16-lead soic_n r-16 adg211akrz-reel ?40c to +85c 16-lead soic_n r-16 adg211akrz-reel7 ?40c to +85c 16-lead soic_n r-16 adg212aknz ?40c to +85c 16-lead pdip n-16 adg212akpz ?40c to +85c 20-lead plcc p-20 adg212akpz-reel ?40c to +85c 20-lead plcc p-20 adg212akr ?40c to +85c 16-lead soic_n r-16 adg212akrz ?40c to +85c 16-lead soic_n r-16 adg212akrz-reel ?40c to +85c 16-lead soic_n r-16 1 z = rohs compliant part. compliant to jedec standards mo-047-aa controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.020 (0.50) r bottom view (pins up) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 0.056 (1.42) 0.042 (1.07) 0.20 (0.51) min 0.120 (3.04) 0.090 (2.29) 3 4 19 18 8 9 14 13 top view (pins down) 0.395 (10.03) 0.385 (9.78) sq 0.356 (9.04) 0.350 (8.89) sq 0.048 (1.22 ) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.020 (0.51) r 0.050 (1.27) bsc 0.180 (4.57) 0.165 (4.19) 0.045 (1.14) 0.025 (0.64) r pin 1 identifier
adg211a/adg212a data sheet rev. c | page 14 of 16 notes
data sheet adg211a/adg212a rev. c | page 15 of 16 notes
adg211a/adg212a data sheet rev. c | page 16 of 16 notes ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10950-0-1 0 /12(c)

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